A study on the role of dielectric and its interface in the performances of Organic Thin-Film Transistor

Abstract

Organic Thin-Film Transistor (OTFT) can be considered one of the building blocks of Organic Large-Area Electronics. The role of this kind of switching device is crucial in the organic information displays field but also in a wide range of possible applications which take advantage of such switching devices. For these reasons, major technology investments have been made to optimize the characteristics related to switching the power status of the pixel in order to obtain sufficient dynamics for a proper representation of moving pictures, movies, etc. In addition to technological and industrial fallouts of OTFT utilization, it should be noted that materials science in Organic Electronics often employs these transistors as an investigation method - an experiment – in order to characterize the physical properties of semiconductors, insulators and interfaces by leveraging device’ principles of operation and physics. The motivation of the present investigation is related to the evidence that gate dielectrics properties and dielectric-semiconductor interface physics are known to govern growth of partiallyordered channel films with a tremendous impact on the morphology of their polycrystalline phase and then to electric performances. Such relationships are still not clearly understood nor fully exploited in a wide spectrum of cases. Keeping in mind that gate insulators can be considered as a key-factor in OTFT device modeling and optimization, the purpose of this thesis work has been the analysis and the interpretation of the role played by such dielectrics and their interface in the organic thin-film transistors performance. The key aspects which have been investigated about dielectrics are the gate leakages and the models to extract the channel current, the relationship between wettability of dielectric surfaces and the growth of pentacene, the channel morphology, charge transport and its thermal activation. In particular, device’ operation regimes and performance parameters have been studied taking into account non-ideal behaviours which can hardly affect physical interpretations of charge transport mechanisms in organic semiconducting films and bring to misleading considerations. In such analysis, the parasitic gate dielectric conduction has been emphasized because it appears appealing both from a scientific point and from an industrial perspective. In fact, gate leakages often appear as a hidden problem in many literature reports and nevertheless they become dominant in technological considerations because they have a relevant impact when working on very thin insulating films or leaky dielectrics like polymers or solution-processed materials because they are responsible of static dissipation in OFET-based circuitry. In order to obtain improved devices, we studied the OTFT performances when varying the dielectric material. We considered the surface wettability as a key factor to be decreased in order to obtain performing channels. Thus, after taking into account standard gate dielectrics at different film thicknesses, and studying mobility in a gate-leakage-aware modeling framework, we acted on the nature and interface of insulators to increase the hydrophobicity and obtain a large-grain growth of pentacene channel semiconductor. In the experimental, among other things, we compared the utilization of highly hydrophobic compounds in gate dielectric layer fabrication to surface conditioning treatments of usual insulating polymers and to the deposition of buffer layers. In the aim to prepare an improved device, we introduced in device’ processing a novel insulating material, an organic-inorganic hybrid material based on a Tetraethyl Orthosilicate / 1H,1H,2H,2H-Perfluorodecyl triethoxysilane solution commonly named “PFTEOS:TEOS”. The abovementioned layer is characterized by perfluoroalkyl units which are responsible of the desired highly hydrophobic properties. It has been solutionprocessed and finally deposited by a spin-coating-based sol-gel technique on the metallic gate layer. Following an optimization path, a thin film (<10nm) of Poly(methyl methacrylate) has been employed to bufferize the PFTEOS:TEOS surface to reduce gate currents. A mobility-morphology trend for analyzed dielectrics in OTFTs has been extrapolated and analyzed denoting PFTEOS:TEOS as an exception to a well-assessed empirical rule. Escaping from obvious considerations about the effect of grain boundaries in channel performances, the singularity of PFTEOS:TEOS has lead to the adoption of thermal activation of charge carriers as an instrument to open to a deeper interpretation of channel defects. Thermal analyses of charge transport activation for the considered samples have been performed showing a general validity of the Meyer-Neldel rule also for hybrid dielectrics. Furthermore, the extraction of energetic parameters in Arrhenius plots applied to static electrical characterizations has revealed differences of maximum mobility trends versus the Meyer-Neldel characteristic Energy (EMN) when comparing polymer dielectric-based OTFTs to PFTEOS:TEOSbased OTFTs. The differences in dielectric/OSC interface appared to be correlated to the isokinetic temperature and activation energy and then to the disorder parameter “:” of the Density Of States in the valence band of the organic channel. Then, instead of considering the contribution of inband density of states of the channel material, the amplitude of the distribution of energetic states has been exploited in the investigation of surface properties and dielectric-specific features remarked. The activation energy analysis showed a trend inversion in the Meyer-Neldel Temperature (TMN)/mobility relationship between PMMA samples and PFTEOS:TEOS samples revealing an effect induced by the very nature of insulator rather than the OSC/dielectric interface on thermally activated processes. The dielectric is then acknowledged to be responsible of a wide range of thermally-activated behaviours in the response of disordered OSC used in OTFTs. Then, thermal analyses have proven to be a key discriminant factor to address non-conventional dielectrics surface-features characterizations in electronic devices able to quantify nanoscopic disorder in polycristalline mediums. In conclusion the behavior of a novel sol-gel gate insulator has been characterized and analyzed comparing it to plain cases and finding an original behavior of mobility/Activation energy which exhibits an inverse (decreasing) trend between energetic disorder and charge transport. This has been completely opposite to trends found for PMMA devices encouraging studying, exploiting and characterizing more in depth PFTEOS:TEOS material for OTFT fabrication purposes. Organic Electronics has still to face some key challenges to assert itself and become competitive in market sectors left still partially unexplored by the inorganic electronic technology. From this point of view, the possibility to exploit dielectric materials singularities to break technological performance trends, united to the availability of second-order modelling techniques both in insulator non-idealities and in charge transport activation can be a non-trivial starting point for further investigations.[edited by author]