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dc.contributor.authorCappetta, Carmine
dc.date.accessioned2020-04-01T06:30:35Z
dc.date.available2020-04-01T06:30:35Z
dc.date.issued2019-02-21
dc.identifier.urihttp://elea.unisa.it:8080/xmlui/handle/10556/4300
dc.identifier.urihttp://dx.doi.org/10.14273/unisa-2505
dc.description2017 - 2018it_IT
dc.description.abstractThe main aim of the present research work is to project and develop very large scale electronic integrated circuits, with particular attention to the ones devoted to image processing applications and the related topics. In particular, the candidate has mainly investigated four topics, detailed in the following. First, the candidate has developed a novel multiplier circuit capable of obtaining floating point (FP32) results, given as inputs an integer value from a fixed integer range and a set of fixed point (FI) values. The result has been accomplished exploiting a series of theorems and results on a number theory problem, known as Bachet’s problem, which allows the development of a new Distributed Arithmetic (DA) based on 3’s partitions. This kind of application results very fit for filtering applications working on an integer fixed input range, such in image processing applications, in which the pixels are coded on 8 bits per channel. In fact, in these applications the main problem is related to the high area and power consumption due to the presence of many Multiply and Accumulate (MAC) units, also compromising real-time requirements due to the complexity of FP32 operations. For these reasons, FI implementations are usually preferred, at the cost of lower accuracies. The results for the single multiplier and for a filter of dimensions 3x3 show respectively delay of 2.456 ns and 4.7 ns on FPGA platform and 2.18 ns and 4.426 ns on 90nm std_cell TSMC 90 nm implementation. Comparisons with state-of-the-art FP32 multipliers show a speed increase of up to 94.7% and an area reduction of 69.3% on FPGA platform. ... [edited by Author]it_IT
dc.language.isoenit_IT
dc.publisherUniversita degli studi di Salernoit_IT
dc.subjectImage processingit_IT
dc.subjectHardware acceleratorsit_IT
dc.subjectFPGAit_IT
dc.titleProject and development of hardware accelerators for fast computing in multimedia processingit_IT
dc.typeDoctoral Thesisit_IT
dc.subject.miurING-INF/01 ELETTRONICAit_IT
dc.contributor.coordinatoreReverchon, Ernestoit_IT
dc.description.cicloXXXI cicloit_IT
dc.contributor.tutorLicciardo, Gian Domenicoit_IT
dc.identifier.DipartimentoIngegneria Industrialeit_IT
dc.contributor.refereePetra, Nicolait_IT
dc.contributor.refereeMartina, Maurizioit_IT
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